| 摘要 |
PURPOSE: A method for manufacturing a self-aligned contact hole of a semiconductor device is provided to improve contact resistance by guaranteeing a lower area of the contact hole, and to improve an electrical characteristic by preventing a substrate from being damaged. CONSTITUTION: A gate structure having a hard mask layer composed of a material having etch selectivity with an interlayer dielectric and a sidewall spacer layer is formed on a semiconductor substrate(20). A planarized interlayer dielectric is formed on the entire structure. The interlayer dielectric in a self-aligned contact region is selectively dry-etched, in which the dry etching process is performed to expose the sidewall spacer layer and to expose the semiconductor substrate.
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