| 摘要 |
PURPOSE: A multiply enhancing a performance and reducing an electric consumption is provided to reduce an electric consumption caused by unnecessary transient and to enhance a calculation velocity by arraying a full adder cell for adjusting an output delay of an adding signal and a carry output signal without an additional delay element. CONSTITUTION: In a multiply being arrayed by a plurality of full adders, a full adder being located in a predetermined row line N, column line M receives an adding signal outputted from a full adder being located in the row line N, column line M-2 and receives a carry signal outputted from a full adder being located in the row line N-1, column line M-1 and performs an adding operation. In addition, the full adder outputs the adding signal of the adding result to a full adder being located in the row line N, column line M+2, and outputs a carry signal of the adding result to a full adder being located in the row line N+1, column line M+1.
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