| 摘要 |
PURPOSE: A virtual channel DRAM is provided to largely reduce testing time of a produced chip by composing of logic so that a data is simultaneously transmitted to n segments from a channel by a specific external command input of one time. CONSTITUTION: The virtual channel DRAM includes a large number of segment portions, a large number of segment selecting portions, a large number of channel portions, a large number of channel selecting portions and a control signal generating portion(130). The large number of segment portions divide the entire of a cell, which is conducted to a bit line by an active command, into a large number of blocks. The large number of segment selecting portions selectively conduct a bit line in a segment of the large number of segments to a data transmitting line. The large number of channel portions temporarily store a data which is transmitted between the bit line, the data transmitting line and a channel bus line. The large number of channel selecting portions selectively conduct a channel bus line in a channel of the large number of channel portions to the data transmitting line. The control signal generating portion generates the first controlling signal which is to selectively conduct the bit line in the segment of the large number of segments to the data transmitting line or simultaneously bit lines in the large number of segments to the data transmitting line.
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