| 摘要 |
PURPOSE: A CMOS RC delay circuit is provided to minimize the number and capacitance of a capacitor in a circuit requiring many delays by performing RC delay using an inverter inverts an output signal from a resistive inverter and feedbacks to an input terminal. CONSTITUTION: A resistive inverter(RINV) has a resistive component, and inverts and outputs an input signal(VIN) to invert. An end of a capacitor(C1) is linked with a ground while the other end is linked with an output terminal of the resistive inverter(RINV). An inverter(INV1) inverts the output signal of the resistive inverter(RINV) and outputs to an input terminal of the resistive inverter(RINV). An inverter(INV2) inverts the output signal of the resistive inverter(RINV) and outputs an output signal(VOUT). Here, the resistive inverter(RINV) is linked with an inverter(INV3) and a resistor(R) in serial, respectively. |
