| 摘要 |
PURPOSE: A block write adjusting circuit make the pulse widths of write signal(WPBEN) and a bank discrimination signal(BBi) in order to reject an error during data write. CONSTITUTION: The block write adjusting circuit includes the first three-phase buffer(B1), the first and second inverters(I1,I2), the second three-phase buffer(B2), the first NAND gate(NAND1), the second NAND gate(NAND2), the third three-phase buffer(B3), the third NAND gate(NAND3), the first NOR gate(NOR1), the second NOR gate(NOR2) the forth inverter(I4) and the fifth inverter(I5). The first three-phase buffer receives input data(DINJB). The first and second inverters are connected in series with PDSF signal. The second three-phase buffer receives color register data(CRIB). The first NAND gate receives mask register data(MRIB), a bank discrimination signal(BBi) and a write signal(WPBEN). The NAND2 receives another bank discrimination signalBBi1 and another write signal(WPBEN1). The third three-phase buffer receives inverted version of the output of the first inverter as a gate driving signal. The first NOR gate receives the output of the third NAND gate. The forth inverter inverts the output of the first NOR gate and outputs as write data(WDi). The fifth inverter inverts the output of the second NOR gate and inverts the write data(WDiB).
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