| 摘要 |
PURPOSE: A semiconductor memory structure having adjacent bit lines sharing a bit line is provided to improve transmission speed of data signal by reducing parasite capacitance. CONSTITUTION: The semiconductor memory structure includes data storages(212,214), an access transistor(NMOS), a memory arrays(211,213), a pre-charger(201), a row decoder(210), a sense amplifier(240), and a plurality of address pins. The access transistor couples a bit line and a word line with the data storages. The memory array includes a plurality of memory cells each of which share one bit line with adjacent memory cell and includes two word lines, respectively. The pre-charger pre-charges the bit lines according to a pre-charge signal. The row decoder selects one word line from plurality of word lines. The sense amplifier amplifies and outputs the data signal stored in the memory cell. The address pins control the operation of the row decoder and column decoder.
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