| 摘要 |
A frame to field converter includes a converter memory and an address generator. The address generator is arranged to repetitively generate a set of line selecting address sequences and to sequentially apply the addresses of successive ones of the line selecting address sequences to the converter memory. Each line selecting address sequence has a first portion of addresses and a second portion of addresses, and no address is repeated in the first portion of each line selecting address sequence. In response to these line selecting addresses, a first group of lines is written into the converter memory in frame order, and the first group of lines is subsequently read out of the converter memory in field order as a second group of lines is written into the converter memory in frame order.
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