| 摘要 |
PURPOSE: A bit line equalization adjusting circuit is provided to perform write operation correctly and quickly even when a bit line load increases due to increase of a memory cell by a unit. CONSTITUTION: The bit line equalization adjusting circuit includes the first delay member(110), the second delay member(120), the first NOR gate(NOR11), the second NOR gate(NOR12), the third delay member(130) and an OR gate(ORG1). The first delay member receives a word line driving signal(ACT). The second delay member receives a word line disable signal(PRE). The first NOR gate receives the output of the first delay member. The second NOR gate(NOR12) receives the output of the second delay member and the output of the first NOR gate and outputs to the first NOR gate. The third delay member receives a write operation pulse(WTP). The OR gate receives the output of the first NOR gate and the third delay member and outputs a bit line adjusting signal(BLEQ).
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