METHOD FOR MANUFACTURING MULTILAYERED METAL INTERCONNECTION OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for manufacturing a multilayered metal interconnection of a semiconductor device is provided to greatly decrease the number of manufacturing s teps by simultaneously etching a via for a plug and a trench for an upper interconnection, and to efficiently perform a manufacturing process by making almost all of the manufacturing processes concentrated on a process for patterning a photoresist layer. CONSTITUTION: A lower metal interconnection(b1) is formed on a structure of a semiconductor substrate. A planarized interlayer dielectric(104,118) is formed on the entire surface having the lower metal interconnection. The first photoresist layer pattern is formed on the substrate. An organic anti-reflecting layer is deposited on the resultant structure having the first photoresist layer pattern, and an entire etching process is performed until the first photoresist layer pattern is exposed. The second photoresist layer is deposited on the resultant structure and patterned. The second and first photoresist layers are patterned. An etching process is performed to simultaneously form a via and an upper interconnection trench by using the photoresist layer pattern and the organic anti-reflecting layer. Metal is filled in the via and the upper interconnection trench, and is polished to simultaneously form a plug(p) and an upper interconnection connected to the lower metal interconnection.