| 摘要 |
PURPOSE: A method for manufacturing a metal interconnection of a semiconductor device is provided to embody a high speed device, by improving a time constant delay characteristic caused by parasitic capacitance of an interlayer dielectric. CONSTITUTION: A substrate(41) where a plurality of the first metal interconnections are formed is prepared. A planarizing insulation layer(43) is formed between the plurality of the first metal interconnections(42) to planarize the surface of the resultant structure. The first insulation layer(44a) and a SiBC layer are sequentially formed. A part of the SiBC layer in an upper portion of the first metal interconnection is etched, and the second insulation layer(44c) is formed to complete an interlayer dielectric(44). The second and first insulation layers are etched to form a damascene pattern composed of a trench(45b) and a via contact hole(45a) by a damascene etching process. A metal layer is buried in the damascene pattern to form a plurality of the second metal interconnections(46).
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