| 摘要 |
PURPOSE: A programmable logic array using single phase clock is provided to execute precharge and evaluation to each circuit using the single phase clock and to remove clock skew and power consumption. CONSTITUTION: The first and second AND planes(300) are provided with input signal and clock signal and code the input signal. The OR plane(310) is provided with the output from the first and second AND planes(300) and the clock signal and codes the output. The inverter(320) is provided with the output from the OR plane(310) and the clock signal and outputs stabilized output signal. The AND plane(300) has a PMOS transistor(301), three NMOS transistors(302,303,304) and an inverter(305). The PMOS transistor has a gate terminal which the clock signal is inputted to and a source-drain path which is formed between power supply voltage and the first node.
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