| 摘要 |
PURPOSE: A method for manufacturing a semiconductor device is to reduce topology difference between a memory region and a logic region in MML(memory merged logic) process to secure process margin of a photolithography and contact etching process for formation of metal contact, thereby increasing production yields and reliability of the device. CONSTITUTION: A word line(42) is formed on a memory region and a logic region of a semiconductor substrate(41). The first interlayer dielectric(43) is formed on the entire structure. A bit line(44) is formed on the first interlayer dielectric in the memory region, and in a portion to be formed of a metal contact of the memory region and the logic region, the first dummy contact pattern and the first dummy pad pattern are formed respectively. The second interlayer dielectric(45) is formed on the entire structure. A capacitor is formed on the second interlayer dielectric in the memory region, and in a portion to be formed of a metal contact of the memory region and the logic region, the second dummy contact pattern and the second dummy pad pattern are formed respectively. The third interlayer dielectric is formed on the entire structure. The metal contacts for substrate, word line, bit line and capacitor are formed by implementing a metal contact process.
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