| 摘要 |
PURPOSE: A wafer level stack package is provided to be capable of shortening an electric signal transfer path and preventing a thickness from becoming thick. CONSTITUTION: The first insulation layer is formed on a lower surface of each semiconductor chip(20) so as to expose a bond pad(21). The first metal pattern(23) is formed on the first insulation layer and has one end connected to the bond pad. The second insulation layer(24) is formed on the first insulation layer so that the other end of the first metal pattern is exposed. The third insulation layer(26) is formed on a lower surface of the lower semiconductor chip(20), and the second metal pattern(27) is formed on the third insulation layer. The fourth insulation layer(28) is formed on the third insulation layer so that two portions of the second metal pattern are exposed. The exposed portions of the second metal pattern become a ball land(27a) and a wire bonding land(27b), respectively. |
