发明名称 METHOD FOR MAKING MENTALIZATION
摘要 PURPOSE: A mentalization forming method is provided to improve an insulation characteristic between the first metal wiring and conductors by forming the first metal wiring contact spacer on a contact hole sidewall after each etch process. CONSTITUTION: A gate oxide film, the first polysilicon(63), the first tungsten silicide(65) and a mask insulation film(67) are formed on a semiconductor substrate(61) and are patterned so as to form a gate electrode. An insulation spacer(69) is formed on a gate electrode sidewall. The first interlayer insulation film(71) is formed on an entire surface of a resultant structure and is annealed. A bit line contact hole is formed so as to expose an active region of the substrate and a bit line connected to the substrate through the contact hole is formed. The bit line consists of the second polysilicon(73) and the second tungsten silicide(75) stacked on the first interlayer insulation film(71), and a mask insulation film and an insulation spacer(77) are formed on the bit line. The second interlayer insulation film(79) is formed on an entire surface, and the first storage electrode conductor(83) is formed so as to be connected to the active region through a contact hole(81). A cylindric storage electrode is formed by forming the second storage electrode conductor(85). After forming a plate electrode(89), the third interlayer insulation film is formed and an etch barrier layer is formed on the third interlayer insulation film. After forming the first contact hole(95), the first insulation spacer(97a) is formed on a sidewall of the first contact hole(95). The second contact hole(99) is formed so as to expose a stack structure of the films(73,75). The second insulation spacer(97b) is formed on a sidewall of the second contact hole(99). The third insulation spacer(97c) is formed on a sidewall of the third contact hole, and the fourth insulation spacer(97d) is formed on a sidewall of the fourth contact hole(103).
申请公布号 KR20010061114(A) 申请公布日期 2001.07.07
申请号 KR19990063600 申请日期 1999.12.28
申请人 HYNIX SEMICONDUCTOR INC. 发明人 BAE, GYEONG JIN;HUH, JUN HO
分类号 H01L27/10;(IPC1-7):H01L27/10 主分类号 H01L27/10
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