| 摘要 |
PURPOSE: A clock noise filter is provided to stabilize the inner operation of a system by making operation so that all of a processor inside of the system have the same clock phase and remove a noise of a frequency band much lower than that capable of being removed with a conventional noise filter, and prevent current consumption from being increased in a standby mode or in a power down mode to reduce current consumption. CONSTITUTION: The clock noise filter includes a latch(300), a phase inverting and delaying block(310), an exclusive NOR gate(320), an invertor(330) and a stabilizing unit. The latch receives an input clock(CLK_IN), a feedback signal fed back from the exclusive NOR gate and a reset signal(RST) and latches the feed back signal according to a clock. The phase inverting and delaying block receives the first output(Q) of the latch and inverts and delays phase. The exclusive NOR gate performs an exclusive NOR operation for an output of the latch and an output of the phase inverting and delaying block. The invertor inverts the second output(QB) of the latch. The stabilizing unit is controlled by an operation stopping signal, fast fixes the output clock in a low at a power down mode and removes the floating state of the output node of the invertor.
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