| 摘要 |
PURPOSE: To provide a semiconductor memory capable of sufficiently securing a reading margin by efficiently using period according to specified CAS latency. CONSTITUTION: The CAS latency is preset before reading. First, an ACT command is inputted and a word line corresponding to a low address is activated. Next, a READ command (CAS) is inputted at the 0-th clock of an internal clock ICLK and a digit line corresponding to a column address is connected with a sense amplifier. At this point of time, a sense amplifier activation signal is validated ('L') without depending of the CAS latency and equalization sense is started. After that, the sense amplifier activation signal is invalidated ('H') two to five cycles later according to the CAS latency and the equalization sense is completed. Then, output operation to transmit a sense result of the sense amplifier to an output pin is performed and the initial data 'D0' becomes usable at the fifth to eighth clock according to the CAS latency.
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