发明名称 INPUT OUTPUT PROTECTION DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS PROTECTION METHOD
摘要 PURPOSE: To provide an input output protection device that is applicable to an input buffer, an output buffer or a two-way buffer of an integrated circuit by only clanging the wiring layout without decreasing the immunity to static electricity adopting shallow junction for its diffusion layer, and employing silicide, and thinning its gate oxide film, following finer constitution of the integrated circuit. CONSTITUTION: A MOS structure is adopted for the protection device and its body is connected to a control circuit being isolated electrically from a semiconductor substrate. Since the potentail of the body equivalent to the base of a parasitic bipolar transistor(TR) is prone to increase when an over-voltage is applied, the protection device turns on at a lower voltage to enhance the immunity to static electricity. Furthermore, since the immunity to static electricity is not dependent on the connection method of the gate, change of the wiring layout permits the semiconductor integrated circuit to be applicable to an input buffer, an output buffer and a two-way buffer. Thus, the buffer size and the chip size can be reduced.
申请公布号 KR20010062768(A) 申请公布日期 2001.07.07
申请号 KR20000082786 申请日期 2000.12.27
申请人 NEC CORPORATION 发明人 MORISHITA YASUYUKI
分类号 H01L23/60;H01L27/02;H01L27/04;H03K19/003;H03K19/0175;(IPC1-7):H01L27/04 主分类号 H01L23/60
代理机构 代理人
主权项
地址
您可能感兴趣的专利