WIDELY FLATTENED MDL AND METHOD FOR MANUFACTURING THE SAME

摘要

PURPOSE: A widely flattened MDL(Merged DRAM in Logic) and a method for manufacturing the same are provided to improve a characteristic of an MDL by forming a widely flattened MDL. CONSTITUTION: A field oxide layer(34) is formed on a semiconductor substrate(32). A transistor is formed on a DRAM cell region and a logic cell region of the semiconductor substrate(34). Spacers(40a,40b) are formed at the sides of gate electrodes(38a,38b). The first interlayer dielectric(42) is formed thereon. A contact hole is formed by performing a photo etching process. A spacer(44) is formed at a sidewall of the contact hole. A pad electrode(46) is formed by depositing and patterning a doped polysilicon layer. The second interlayer dielectric(48) and the third interlayer dielectric(50) are deposited thereon. The third interlayer dielectric(50) is removed from the DRAM cell region. A contact hole is formed by etching the second and the first interlayer dielectrics. A spacer(52a) is formed at a sidewall of the contact hole. A spacer is formed at a boundary of the DRAM cell region and the cell region. A conductive layer(54) is formed on the whole structure. A material layer(56) is formed on the conductive layer(54). A photoresist pattern(58) is formed on the material layer(56). A polysilicon layer(60) is formed on a spacer formed by the conductive layer(60) and the material layer(56). A dielectric layer(62) is formed thereon. An upper electrode is formed by depositing and patterning the doped polysilicon layer. The fourth interlayer dielectric(66) is formed thereon. The fourth interlayer dielectric(66) is flattened by performing a CMP(Chemical Mechanical Polishing) process.