CIRCUIT OF CONTROLLING RESET SIGNAL

摘要

PURPOSE: A circuit of controlling reset signal is provided to supply the control unit with a reset signal for a set period and to maintain the reset signal during the time needed to initialize the system. CONSTITUTION: In the circuit of controlling reset signal, a binary counter(100) receives a signal of a valid address having a low level value through an inverter as a medium and divides the clock signal by a preset control signal. A multi-vibrator(110) receives the divided clock signal. A pulse width adjusting unit(120) maintains the pulse width of the signal generated at the multi-vibrator(110) for a set period. A program-enable logic unit(130) decodes the signal from the pulse width adjusting unit(120). A control unit(140) initializes the system after receiving the reset signal from the program-enable logic unit(130).