| 摘要 |
PURPOSE: An interrupt processor reduced interrupt response time is provided to increase an interrupt processing speed by performing a real interrupt service routine, thereby reducing an interrupt response time. CONSTITUTION: A PIARF(programmable interrupt address register file,100) stores an interrupt address relevant to the first address of a program in which each interrupt service routine is stored. A PICRF(programmable interrupt code register file,120) stores the first command code of each interrupt service routine. A multiplexer(140) responds to an interrupt enable signal, and selectively outputs an interrupt address of the PIARF(100). A multiplexer(160) selectively outputs a command code of the PICRF(120). The address outputted from the multiplexer(140) is outputted to a program counter(180). The code outputted from the multiplexer(160) is outputted to a command register(200). The code of the PICRF(120) designated by an interrupt flag is loaded to the command register(200).
|
