发明名称 INFORMATION DETECTING CIRCUIT WITH BUILT-IN ADAPTIVE EQUALIZER AND OPTICAL DISK DEVICE USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide an information detector with a digital PLL circuit having a wide margin the loop delay of which is short and following secular change, and an optical disk device. SOLUTION: Information is detected by A/D converting a reproduction signal by a clock with frequency higher than that of a channel clock, digitally equalizing A/D conversion output by the same clock, performing re-sampling from digital equalization output by the PLL circuit applying an interpolation circuit, re-sampling the A/D conversion output by a second interpolation circuit after delaying it by the same quantity as that of a digital equalizer, using information about the PLL circuit for an interpolating position of the second interpolation circuit, a tentative tap coefficient is generated by inputting interpolation information before and after equalization in a tap coefficient controller, feeding back the tentative tap coefficient by converting it into operation rate of the digital equalizer by a rate collecting circuit, inputting interpolation output of equalizer output in a binarization circuit.
申请公布号 JP2001184795(A) 申请公布日期 2001.07.06
申请号 JP19990367483 申请日期 1999.12.24
申请人 NEC CORP 发明人 HONMA HIROMI
分类号 G11B7/005;G11B20/10;H04L7/02;H04L7/033;(IPC1-7):G11B20/10 主分类号 G11B7/005
代理机构 代理人
主权项
地址