发明名称 PRODUCING METHOD FOR MULTILAYER PRINTED WIRING BOARD
摘要 <p>PROBLEM TO BE SOLVED: To provide a producing method for a multilayer printed wiring board which reduces void, warp or twist which easily occur at the spot of a low residual copper rate on an inner layer circuit board. SOLUTION: Concerning the producing method for a multilayer printed wiring board constituted by laminating and molding through a prepreg outer layer metal foil and an inner layer circuit board having mutually separated circuit groups on the same face, a dummy printed circuit board with which a similar pattern is formed in the area with no circuit on the inner layer circuit board is placed at the stage internal position of a press, heated and pressed.</p>
申请公布号 JP2001185849(A) 申请公布日期 2001.07.06
申请号 JP19990368852 申请日期 1999.12.27
申请人 HITACHI CHEM CO LTD 发明人 NARISAWA HIROSHI
分类号 H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/46
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