| 摘要 |
PURPOSE: A bit stream processor is provided to reduce a performance loss by adopting a FIFO register structure suitable for a bit stream processing, and by providing a bit pattern successively arrayed. CONSTITUTION: A program sequence(10) is a block for controlling a sequence of a bit stream processing. A bit stream receiver(20) inputs bit stream data, and converts the data into a data format capable of being processed in a data path(30). The data path(30) takes charge of an address calculation and data execution. A FIFO(First In First Out) control unit(40) forms a bit pattern requested by the data path(30) through an interface with the data path(30). An address decoder(60) is a general decoding logic, and performs a target selection. A serial interface(50) outputs data in which the bit stream processing is completed in parallel.
|
