发明名称 TEST CIRCUIT OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a test circuit of a semiconductor device in which fault can be recognized even when a switching circuit and a memory are broken down simultaneously, when output from plural memories incorporated in each semiconductor device is switched and tested using the same signal for test. SOLUTION: This test circuit is provided with a memory input selector 3 switching a signal at the time of normal operation or a signal for test and inputting it to each memory 1, a memory output selector 8 switching output of each memory and outputting it, a test control circuit 7 controlling supply of a signal for test for a memory input selector and respective switching of each selector, and a first logic circuit 9 inserted between a memory and a memory output selector. The first logic circuit adds change being different for each memory to output signal of plural memories.
申请公布号 JP2001184900(A) 申请公布日期 2001.07.06
申请号 JP19990370697 申请日期 1999.12.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIDA YOICHIRO
分类号 G01R31/28;G11C29/00;G11C29/02;H01L21/66;(IPC1-7):G11C29/00 主分类号 G01R31/28
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