发明名称 BUFFER CONTROL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the memory capacity of a buffer memory. SOLUTION: A differential calculating circuit 22 acquires the held data amount of a correspondent buffer memory 4 at intervals of a fixed time, finds a differential from the last data amount and provides a bit rate during a relevant period. According to this bit rate, a priority change circuit 24 sets the higher priority to the buffer memory 4 of the higher bit rate. On the basis of this set priority, an arbitration circuit 18 selects the buffer memory 4. Therefore, the high priority is dynamically set to the buffer memory 4 to which data is frequently inputted at the time of operation, the wait time of such a buffer memory is shortened and the held data can be frequently outputted. As a result, even when memory capacity is small, overflow does not occur and the memory capacity of the buffer memory 4 can be reduced.
申请公布号 JP2001184302(A) 申请公布日期 2001.07.06
申请号 JP19990365815 申请日期 1999.12.24
申请人 NEC CORP 发明人 OIKAWA MASAHIKO
分类号 G06F3/12;G06F12/00;G06F13/362;G06F13/38;H04N1/21;(IPC1-7):G06F13/38 主分类号 G06F3/12
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