| 摘要 |
PROBLEM TO BE SOLVED: To provide an image reduction device reducing an image of a video signal adopting a progressive scanning system that decreases the power consumption by employing a decreased clock frequency. SOLUTION: A serial/parallel conversion circuit 101 converts an input video signal S1 adopting the progressive scanning system into a parallel signal in the unit of two lines. A signal selection circuit 103 selects two out of an odd numbered line signal, its delay signal and an even numbered line signal and gives the selected signals to an interpolation arithmetic circuit 104. When a magnification setting circuit 107 sets a reduction rate (m), a control coefficient generating circuit 108 generated a control coefficient (k) in response to the reduction rata (m), and an interpolation coefficient calculation circuit 109 calculates an interpolation coefficient (w). The interpolation arithmetic circuit 104 applies an interpolation arithmetic operation to an output signal from a selection circuit 103 in response to the interpolation coefficient (w). Thus, the circuits other than the serial/parallel conversion circuit 101 can be operated at a clock signal CLK2 with a low frequency outputted from a clock generator 110.
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