| 摘要 |
PROBLEM TO BE SOLVED: To provide a modification method of a semiconductor integrated circuit which can cut the cost and time for a test by reducing a test pattern by effectively using a spare cell which is originally used only for circuit modification. SOLUTION: A circuit modification cell is subjected to wiring to be used for improving controllability and observability of a combinational circuit of user logic during a test of a scan path method, a mask pattern of all the layers for manufacturing a semiconductor integrated circuit is prepared, a circuit modification cell is connected once more to a portion which requires a new circuit modification cell through circuit modification in accordance with later circuit modification, and a mask pattern of a wiring layer alone is prepared once more.
|
