METHOD AND DEVICE FOR DESIGNING INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a method and a device for designing an integrated circuit for considering delay at every register in a clock line, preventing the increase of the number of gates by the insertion of a delay buffer, enlarging holding/setup margins and preventing malfunction. SOLUTION: Timing is analyzed by using net information of a circuit including the plural registers (step 81). Information obtained by detecting the register of the small holding margin or setup margin and adding an attribute to the register is generated (step S2). A CTS processing for distributing clocks among the respective registers by using net information by buffering is conducted (step 3). In the CTS processing, the distribution of the clocks is optimized so that the margin is enlarged by distributing the clocks of timing corresponding to the margins of the registers so that the clock of fast timing is supplied from the other register to the register to which the attribute is added.