| 摘要 |
PROBLEM TO BE SOLVED: To settle a problem that the scale and power consumption are increased for a circuit which produces two clock signals of different frequencies by means of two PLL circuits and that the power consumption of the circuit is increased by the frequency when a single PLL circuit is used. SOLUTION: This clock generator includes an N-phase clock PLL generation circuit 1 which generates the N-phase clock signals having the phases shifted by a prescribed period, an N-phase clock selection circuit 2 which selects one of N-phase clock signal and a ring counter 3 which outputs a selection signal to the circuit 2 to indicate the clock signal to be selected. Then the counter 3 switches successively the N-phase clock signals which are selected by the circuit 2 to produce the clock signals having the frequencies different from the N-phase clock signals.
|
