| 摘要 |
PURPOSE: An apparatus for connecting ATM(Asynchronous Transfer Mode) cell processors to each other in series is provided to simplify the interface between the processors and expand the distance therebetween, by serializing a parallel UTOPIA(Universal Test and Operation PHY Interface for ATM) bus, and thereby reducing the number of connection signals of the bus. CONSTITUTION: A control circuit(210) extracts parallel data loaded on the parallel UTOPIA bus, and then transmits it to a serial conversion part(220). The serial conversion part(220) converts the parallel data extracted by the part(210) to a serial data signal. A serial parallel conversion part(230) the serial ATM cell data received from the serial conversion part(220) to data having a UTOPIA bus format. A FIFO(First In First Out) register(240) stores data until an ATM layer processor(300) and a physical layer processor(100) access the data, which is received as a parallel signal under the control of the control circuit(210).
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