MULTI-BANK, FAULT-TOLERANT, HIGH-PERFORMANCE MEMORY ADDRESSING SYSTEM AND METHOD

摘要

The present invention provides a multi-bank memory addressing system and method which generally provides no bank conflicts for stride 1 access patterns and infrequent bank conflicts for other access patterns of interest. In one embodiment, a memory device is provided having a plurality of memory banks comprising a plurality of addressable memory locations. Each memory location has a logical address and a corresponding physical address, the physical address comprising a memory bank number and a local address within the memory bank (2). The memory device comprises an address system, including an address translation unit (1), that derives, for each logical address, the corresponding physical address.