| 摘要 |
An I/O port can synchronize the transmission of data on both the rising edge and falling edge of a system clock signal (SCLK) by matching the duty ratio of the internal clock (MCLK) with the duty ration of the system clock SCLK. This is accomplished by individually delaying both the rising edge and falling edge of the input clock SCLK. By individually delaying both the rising edge and falling edge, the rising edge and falling edge of the system clock SCLK and internal clock MCLK are synchronized. This synchronization ensures that data can be accurately transmitted on both edges of the clock signal. To accomplish this, an I/O port for a CPU has an input port configured to receive a system clock signal, and a digital delay locked loop configured to synchronize a rising edge of an internal clock signal with a rising edge of the received system clock signal and configured to synchronize a falling edge of the internal clock signal with a falling edge of the received system clock signal. The digital delay locked loop (DLL) includes a phase generator configured to receive the system clock signal and to generate a rising edge signal indicative of the rising edge of the system clock signal and to generate a falling edge signal indicative of the falling edge of the system clock signal. The DLL may also include a first series of delay stages configured to delay the rising edge signal and a second series of delay stages configured to delay the falling edge signal, and a clock generator configured to create the internal clock signal from the delayed rising edge signal and delayed falling edge signal. One or more second clock generators configured to create intermediate signals may also be included. The intermediate signals from these second clock generators are used to determine whether the first series of delay stages is delaying the rising or falling edge signals by an excessive amount.
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