| 摘要 |
PURPOSE: A method for manufacturing a DRAM of a semiconductor device is provided to simplify a manufacturing process for a high integrated dual poly-gate DRAM more than 4Gbit by forming a cell of a gate length less than 0.1 micro meter as a spacer type gate. CONSTITUTION: A field oxide layer and the first oxide layer are formed on a substrate(110). The first oxide layer of a cell region is etched partially. A gate oxide layer is formed on the structure. A doped poly layer and a tungsten silicide layer are formed thereon. A spacer type gate is formed at a sidewall of the first oxide layer. An LDD ion implanting process is performed on the cell region. The second oxide layer and the first nitride layer are deposited thereon. A PMOS region of a CMOS region is exposed by performing a dry etching process. The second gate oxide layer(152) is formed on an opened PMOS region. The second poly layer(162) and the second tungsten silicide(172) are deposited thereon. A PMOS photoresist pattern is formed on the second tungsten silicide(172). A PMOS gate is formed by performing the dry etching process. A spacer is formed on the spacer type gate. An NMOS region of the CMOS region is opened. An NMOS gate is formed by performing the dry etching process. The third oxide layer is deposited thereon. The third poly layer(163) is formed by performing an epitaxial growth process. The third oxide layer of the CMOS region is removed. N-/P- ions are implanted the NMOS region and the PMOS region, respectively. The fourth oxide layer and the second nitride layer are deposited thereon. A spacer is formed at the PMOS gate and the NMOS gate. N+/P+ ions are implanted on the PMOS region and the NMOS region. The fifth oxide layer(135) is deposited thereon. Bit line contacts are formed on the cell region, the gate of the CMOS region, and the active region, respectively. A bit line and a capacitor are formed.
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