| 摘要 |
PURPOSE: A board bias circuit is provided to increase the reliability of a low voltage circuit by preventing a loss generated by the threshold voltage of a switching element. CONSTITUTION: When a CLK reaches to a VDD level, the gate voltage of a PMOS transistor(206) is VDD-Vtp210. At this time, /CLK reaches to a VSS level, and the source voltage of a PMOS transistor(220) is -Vtp220. The gate voltage of the PMOS transistor(210) is -Vtp210. Because the gate voltage of the PMOS transistor(210) is much smaller than that of the PMOS transistor(210), the Vtp210 value becomes so low, and the voltage of a capacity reaches to VDD. When a CLK reaches to the VSS level, the voltage of the capacity(228) is inverted, and -VDD is applied to each gate of the PMOS transistor(206) and the PMOS transistor(208). For this reason, the PMOS transistor(206) is turned on, and the PMOS transistor(208) is turned off, and the voltage of a capacity(204) reaches to VDD level. At this time, because the NMOS transistor(208) is turned off, charges of the capacity(204) is not transferred to a load capacity(222). When the CLK reaches to a VDD level again, the voltage of a capacity(204) is inverted, and the charges of the capacity(204) is transferred to the NMOS transistor(208).
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