CLOCK SKEW ADJUSTING METHOD AND ITS MEDIUM

摘要

PROBLEM TO BE SOLVED: To adjust a clock skew for an outer system device by a clock skew adjusting method for a device internal circuit. SOLUTION: A checking of whether a maximum delay of an input route to a flip-flop connected with an input terminal is less than a maximum delay to which a clock skew adjustment in a clock distribution is added or not is performed and a checking of whether a maximum delay time for all flip-flop which can directly be attained on an output route from the flip-flop is less than a maximum delay to which a clock skew adjustment in the clock distribution is added or not is performed. An allowance for the delay generated by the clock distribution is calculated, an element or a wire is so inserted in the clock route of the flip-flop as the results to be in a less delay range than the allowance value, and a maximum delay time from the terminal is adjusted.