发明名称 |
PRIORITIZED BUS REQUEST SCHEDULING MECHANISM FOR PROCESSING DEVICES |
摘要 |
A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
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申请公布号 |
WO0148617(A2) |
申请公布日期 |
2001.07.05 |
申请号 |
WO2000US32022 |
申请日期 |
2000.11.22 |
申请人 |
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发明人 |
HILL, DAVID, L.;BACHAND, DEREK, T. |
分类号 |
G06F12/00;G06F12/08;G06F13/16;G06F13/18;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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