发明名称 Multilevel storage semiconductor memory read circuit
摘要 In a read circuit, a sense amplifier amplifies a current flowing in a cell and determining whether the cell is an ON cell or an OFF cell. A latch circuit group consists of latch circuits latching output data from the sense amplifier. An encoder circuit converts the latched data into binary data. An output circuit outputs the encoded data. A stop and correction circuit stops an operation of a first-stage or third-stage sense amplifier circuit based on an output result of a second-stage latch circuit and applies a signal expected to be outputted from the sense amplifier which is being stopped, as a latch input signal L0.
申请公布号 US2001006480(A1) 申请公布日期 2001.07.05
申请号 US20000748035 申请日期 2000.12.22
申请人 NEC CORPORATION 发明人 SATO AKIRA
分类号 G11C16/06;G11C11/56;G11C16/02;(IPC1-7):G11C7/00 主分类号 G11C16/06
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