| 摘要 |
A method for processing data in a processor having a processor core for processing a command in a pipeline form, a program counter for storing a memory address of a command to be fetched, decoded and executed by the processor core; a program counter generation logic for increasing a program counter value and outputting it to the program counter, and a memory for storing a program including a repeat block, comprising the steps of: setting a repeat count value; executing a repeat block command to set a repeat ending address and a repeat starting address, and decoding a first command of the repeat block and fetching a second command of the repeat block; comparing the repeat ending address and a memory address of the second command to identify whether they are identical to each other; checking whether the first command is a command for nonlinearly changing an executing order of a program if the repeat ending addresses and the memory address of the second command are identical to each other; and storing the memory address of the second command while not reducing the repeat count value if the first command is a command for nonlinearly changing the executing order of the program.
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