| 摘要 |
A fast Hadamard transform device is provided which prevent from increasing of circuit scale and shorten a developing TAT even if the number of bits to be operated. The device includes n of shift register units and n/2 of butterfly computation units. Input data are entered to the shift register units in response to a signal and data stored in the shift register units are supplied as quantized data by providing a signal for each "log2n*(p+log2n)" clocks.
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