发明名称 |
Electronic parts placement method and a computer readable medium having an electronic parts placement program |
摘要 |
When gates are placed on a chip, an average delay budget per stage of the gate is calculated from a target machine cycle time and the number of logic gate stages between an initial point flip-flop and a terminal point flip-flop, a wire length limitation of a net of each stage is calculated from the average delay budget and delay characteristics of the gate of each stage, and the gates are placed by using the wire length limitation as a target function.
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申请公布号 |
US2001007145(A1) |
申请公布日期 |
2001.07.05 |
申请号 |
US20000725126 |
申请日期 |
2000.11.29 |
申请人 |
SAKAGAMI TOMONARI;MOGAKI MASATO;MIYAMARU IKUTANE |
发明人 |
SAKAGAMI TOMONARI;MOGAKI MASATO;MIYAMARU IKUTANE |
分类号 |
H01L21/82;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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