| 摘要 |
PURPOSE: A duty cycle correcting circuit is provided to reduce an exiting time of a nap mode and elongate a nap mode time, by digitizing analog duty information of a clock in a nap mode so as to store the information even though the nap mode is longer. CONSTITUTION: A duty cycle correcting part(430) corrects a duty cycle of a clock signal received at a normal mode of operation and stores in a capacitor a duty cycle of a clock input signal previously corrected at a nap mode of operation. An analog-to-digital converter(520) converts an analog signal from the duty cycle correcting part into a digital signal according to the first control signal(en_adc). The digital converter maintains a previous value regardless of an input signal when the first control signal is disabled. A digital-to-analog converter(530) converts the digital signal from the analog-to-digital converter into an analog signal according to the second control signal(en_dac). The digital-to-analog converter turns off an output signal regardless of an input signal when the second control signal is disabled. A controller(510) generates the first and second control signals(en_adc,en_dac) according to whether the nap mode of operation is executed.
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