| 摘要 |
PURPOSE: An output buffer circuit is provided to reduce loading of a data output line for operating with high speed by independently receiving data without sharing the data output line of memory cell blocks and outputting the data to a data output pad. CONSTITUTION: The output buffer circuit includes a precharge portion(1), the first and second switching portions(2,3), a high input portion(4), a low input portion(5) and an output portion(6). The output buffer circuit outputs the output data(Dout1,Dout2) of two memory cell blocks to an outside through a data output pad(DQ PAD). The precharge portion precharges the first and second data input lines(DIL1,DIL2) respectively receiving the output data to a high level. The first switching portion applies a voltage of a low level to the second signal input line(SIL2) according to the logic level of an output enable signal or connects the first signal input line(SIL1) with the second signal input line. The second switching portion applies a voltage of a high level to the first signal input line according to the logic level of the output enable signal(OE) or connects the first signal input line with the second signal input line. The high input portion applies the voltage of a high level to the first signal input line according to the voltage level of the first and second data input lines. The low input portion applies the voltage of a low level to the second signal input line according to the voltage level of the first and second data input lines. The output portion applies the voltage of a high level of a low level to the data output pad according to the voltage level of the first and second data input lines.
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