发明名称 WAFER SCALE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
摘要 PURPOSE: A wafer scale package is provided to prevent an electrical interference between lead wires and harden the strength of the lead wires. CONSTITUTION: A wafer scale package includes a wafer(51) in which a plurality of chip pads(53) are formed. An insulating tape(55) of a given pattern is attached to the top of the wafer(51). A plurality of lead wires(59) are adhered to lands(73) of a printed circuit board(71) when a tip portion in the middle of the lead wires(59) is mounted to the printed circuit board(71). Both ends of the lead wires(59) are bonded to respective chip pads(53) and the insulating tape(55). An insulating coating layer(61) fills the space between the lead wires(59) and is formed at a portion where the lead wires(59) arte bonded so that insulation between neighboring lead wires(59) can be made. A plating layer(63) is formed at the tip portion of the lead wires(59) in order to increase the strength of the lead wires(59).
申请公布号 KR20010055801(A) 申请公布日期 2001.07.04
申请号 KR19990057111 申请日期 1999.12.13
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHA, GI BON
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
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