TEST MODE SIGNAL GENERATING CIRCUIT USING CLOCK AND RESET PINS OF SEMICONDUCTOR CHIP

摘要

PURPOSE: A test mode signal generating circuit is provided to prevent increasing of unnecessary pins and establish various test modes. CONSTITUTION: A decoder part(22) decodes an input signal(IN) received from one or more input pins to generate a test signal(TEST). A counter part(24) counts a falling edge of a chip reset signal(RESET) in a high-level period of a clock signal(CLK) received through a clock pin and outputs a counted value(CNT). A signal output part(26) receives the test signal(TEST) from the decoder part(22) and generates a test mode signal(TESTMODE) having a low-to-high transition when the counted value is over a predetermined threshold value.