| 摘要 |
PURPOSE: An interface circuit between ATM devices using a dual port FIFO is provided to design an FPGA having a dual port FIFO capable of adjusting a capacity based on the amount of traffics and comply with a UTOPIA standard between commercial ATM devices which satisfy a UTOPIA level 1 of an ATM forum. CONSTITUTION: In the case of an upstream data path, an upstream FIFO(11) is a dual port which has a variable capacity stores a cell outputted from an upstream transmitter(10). An upstream cell controller(12) receives a cell_next_tx from the upstream transmitter(10) and a cell_next_tx from the upstream receiver, counts the cells stored in the upstream FIFO(11) through an internal cell counter, writes the cell from the upstream transmitter(10) into the upstream FIFO(11), reads the cells stored in the upstream FIFO(11) by the upstream receiver and controls the read and write by the cell unit. An upstream receiver(13) outputs a read enable to the upstream FIFO(11) based on a cell_rdy_rx outputted from the upstream cell controller(12), reads the data from the upstream FIFO(11) and one cell from the upstream FIFO(11), outputs a cell_next_tx to the upstream cell controller(12). In the case of the downstream data path, a downstream cell controller(22) receives a cell_next_tx from the downstream transmitter(20) and a cell_next_rx from the downstream receiver and counts the cells stored in the downstream FIFO(21) based on the internal cell counter.
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