| 摘要 |
PURPOSE: A double data rate synchronous(DRAM) is provided to output read data synchronized with a CAS(Column Address Strobe) latency in order to output data synchronized with data clock without clock skews. CONSTITUTION: The DDR SDRAM includes the first data output control signal generator(100) and the second data output control signal generator(200). The DDR(Double Data Rate) SDRAM(Synchronous DRAM) according to the present invention uses a DLL(delay locked loop). The first data output control signal generator receives the output active signal including CAS latency signal and a burst length information and generates a data output control signal based on an enable mode of the DLL. The second data output control signal generator receives the second output activation signal which leads the first output activation signal by one clock and generates a data output control signal based on the disable mode of the DLL. The first data output control signal generator further includes a NAND gate as well as a CMOS transmission gate.
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