| 摘要 |
PURPOSE: A method for manufacturing semiconductor memory is provided to prevent an etching of a nitride layer which is important to decide an etching rate and quantity in a gate sidewall formation of a peripheral circuit area, secure an etching margin at a contact hole formation process, and improve the process reliability by depositing an oxide on a nitride hardmask used for forming a bitline plug, forming a nitride sidewall on a side of the nitride layer and an oxide layer. CONSTITUTION: A process forms a gate included in a gate of a cell transistor and a peripheral circuit on a substrate(1) defining a cell area and the peripheral circuit area, to deposit a polycrystal silicon on the whole substrate(1), a nitride layer(4), a first oxide layer on the polysrystal silicon, and an exposed gate in an orderly manner. The process forms the first oxide layer and the nitride(4) stacked pattern located on the polycrystal silicon area contacting the common source of the cell gate by patterning the first oxide layer and the nitride layer(4) deposited through a photoetching process, and then deposits again the nitride(4) and forms a nitride layer sidewall(9) on the side of the first oxide layer and the nitride layer stacked pattern by using dry etching the nitride(4), to eliminate the exposed polycrystal silicon through the etching process by utilizing the oxide layer and the nitride layer sidewall(9) as etching mask, and form a bitline plug contacted to a bitline. A process deposits a second oxide layer on the structure, forms a sidewall on the side of the gate formed on the peripheral circuit area by using the dry etching, deposits a third oxide layer on the structure, and exposes the bitline plug by forming a contact hole on a part of the first and third oxide layers and the nitride layer(4).
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