发明名称 |
Synchronous semiconductor memory device having input buffers and latch circuits |
摘要 |
A synchronous semiconductor memory device having a plurality of external signal input buffer and a plurality of latch circuits, includes: a clock buffer for receiving an external clock signal to generate a buffered clock signal; a chip select buffer for receiving an external chip select signal and the buffered clock signal from said clock buffer to generate a buffered chip select signal, an inverted buffered chip select signal and a latch control signal, wherein the latch control signal is activated when the external clock signal is at the rising edge and the external chip select signal is low; a plurality of external signal buffers for receiving external signals to generate buffered signals and inverted buffered signals; and a plurality of latch circuits for latching and outputting the buffered signals and the inverted buffer signals to an internal logic circuit in response to the latch control signal.
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申请公布号 |
US6256260(B1) |
申请公布日期 |
2001.07.03 |
申请号 |
US20000570729 |
申请日期 |
2000.05.12 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
SHIM YOUNG-BO;KANG WOO-SOON |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C8/06;G11C11/4093;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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