Method for hidden DRAM refresh

摘要

An apparatus comprising a memory and a logic circuit. The memory may comprise a plurality of storage elements configured to read and write data in response to a first internal address signal and a second internal address signal. The logic circuit may be configured to generate either (i) the first and the second internal address signals when accessing one of the storage elements for a read or a write operation or (ii) the first internal address signal when accessing one of the storage elements for a read refresh operation.