发明名称 Bus optimization with read/write coherence including ordering responsive to collisions
摘要 The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.
申请公布号 US6256713(B1) 申请公布日期 2001.07.03
申请号 US19990303365 申请日期 1999.04.29
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 AUDITYAN SRINATH;HARDAGE, JR. JAMES NOLAN;PETERSEN THOMAS ALBERT
分类号 G06F12/00;G06F12/08;G06F13/18;(IPC1-7):G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址